GRID: 32 x 32 x 32 per processor(tile) 
ZEUS-MP (10 Steps) 

COMMENT: The tiles are all in a row in this experiment (1-D Domain decomposition).  
         Since the tile surface-to-volume ratio is constant, the ratio of  
         communication to computation is independent of the 
         number of processors N, just as it is for a 3-D decomposition. 
         Thus, speedups should be similar for 2x2x1 and 2x2x2 tile layouts. 
 
                                                                            Speedup/
Processors  Layout Wall Clock tused(s) Zone-Cycles/sec MFLOPS  C90s Speedup Processor 
    1       1x1x1     8.69      8.57        37992       34.78   .32   1.00    1.00 
    2       2x1x1     8.83      8.71        74632       68.31   .62   1.96    0.98 
    4       4x1x1     9.05      8.98       145636      133.31  1.21   3.83    0.96 
    8       8x1x1    10.11      9.92       261327      239.21  2.18   6.87    0.86