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SGI Power Challenge Array (4x16 R8000 CPUs)
| These machines are connected via
HIPPI with a full crossbar switch. These tests were performed in single-user mode. All routines were compiled with: f77 -c -O3 -g3 -w
GRID: 32 x 32 x 32 per processor(tile)
Zone-Cycles/ Speedup/
Processors Layout Wall Clock tused(s) sec MFLOPS C90s Speedup Processor
1 1x1x1 4.68 4.64 70334 61.47 0.32 1.00 1.00
2 2x1x1 5.03 4.97 130881 114.39 0.60 1.86 0.93
4 2x2x1 5.00 4.95 263300 230.13 1.21 3.74 0.94
8 2x2x2 5.33 5.25 495453 433.04 2.28 7.04 0.88
16 4x2x2 6.26 6.03 864381 755.50 3.98 12.29 0.77
32 4x4x2 16.50 16.07 648345 566.68 2.98 9.22 0.29
64 4x4x4 45.61 42.76 467040 408.21 2.15 6.64 0.10
GRID: 64 x 64 x 64 per processor(tile)
Zone-Cycles/ Speedup/
Processors Layout Wall Clock tused(s) sec MFLOPS C90s Speedup Processor
1 1x1x1 39.80 39.38 66115 54.11 0.18 1.00 1.00
2 2x1x1 40.80 40.34 129099 105.65 0.36 1.95 0.98
4 2x2x1 41.69 41.24 252549 206.67 0.71 3.82 0.95
8 2x2x2 45.65 45.07 461475 377.65 1.29 6.98 0.87
16 4x2x2 68.46 66.65 621333 508.47 1.74 9.40 0.59
32 4x4x2 75.70 73.13 1126290 921.70 3.15 17.04 0.53
64 4x4x4 113.49 109.70 1503090 1230.06 4.20 22.73 0.36
GRID: 128 x 64 x 64 per processor(tile) (4 or 10 steps)
Zone-Cycles/ Speedup/
Processors Layout Wall Clock tused(s) sec MFLOPS C90s Speedup Processor
1 1x1x1 75.50 74.68 69705 54.16 0.33 1.00 1.00
2 1x1x2 75.50 74.57 139601 108.46 0.67 2.00 1.00
4 1x2x2 76.69 75.79 274691 213.42 1.31 3.94 0.99
4 1x2x2 76.78 75.92 274217 213.51 1.31 4.00 1.00
8 2x2x2 45.70 45.12 461674 359.46 2.21 6.73 0.84
16 2x4x2 148.44 129.34 640063 498.36 3.05 9.34 0.80
32 2x4x4 149.24 140.89 1169500 910.58 5.57 17.06 0.53
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The Computational Astrophysics Data Analysis Center